FIG. 12 is a diagram showing an architecture of a memory-cell array in a dynamic random-access memory (DRAM) as a typical conventional semiconductor memory device. As shown in the figure, memory-cell arrays (or memory banks) 206 each comprising a number of memory cells laid out to form a matrix are separated from each other in a bit-line direction by sense-amplifier units 207. The memory-cell arrays 206 are separated in a word-line direction by a word-line shunting area 208 in the case of a word-line shunt system or by a sub-word driver area 208 in the case of a split word-line architecture.
Data is read out and latched in the sense-amplifier units 207. Column-select lines (CSL) 209 are activated in accordance with a column address, causing the data to be output from the sense-amplifier units 207 to pairs of local I/O lines 210. The pairs of local I/O lines 210 are connected to a pair of global I/O lines 211 which is located on the word-line shunting area or the sub-word driver area 208 to form a data route in a read/write operation.
A switch 212 is provided between each of the pairs of local I/O lines 210 and the pair of global I/O lines 211. Only a single switch 212 associated with a selected memory-cell array 206 is turned on. Normally, the switch 212 is located at the intersection of the sense-amplifier unit 207 and the word-line shunting area or the sub-word driver area 208. In a CSL system, the pair of local I/O lines 210 associated with a selected memory-cell array 206 is connected to the pair of global I/O lines 211. If the switches 212 are not provided, all the pairs of local I/O lines 210 are connected to the pair of global I/O lines 211, increasing the load on a data bus. In addition, it is generally necessary to set the precharge potentials of selected pairs of local I/O lines 210 and deselected pairs of local I/O lines 210 at different values from the access-speed point of view.
In recent years, there has been a trend of increasing the number of bits per word to keep up with increases in capacity. Demands for DRAMs with an x32/x64/x128 word structure are anticipated. Demands for multi-bank and multi-bit specifications are also foreseen for synchronous DRAMs. To meet such demands, it is necessary to incorporate a number of data buses from memory-cell arrays. In this case, it is necessary to design architectures of memory-cell arrays and data buses that do not require an increase in memory-cell-array area, that reduce the number of activated memory-cell arrays by as many as possible, and that reduce the amount of consumed current at the same time
Meeting such demands with a memory-array architecture like the one shown in FIG. 12 would increase the loads connected to the column-select lines and the global I/O signal lines. In addition, the memory-architecture cannot sufficiently keep up with increases in bit count and memory-bank count. The present invention addresses these problems.